This invention relates to programmable logic resources. More particularly, this invention relates to providing a dedicated crossbar and/or barrel shifter block on programmable logic resources.
Programmable logic resources, such as programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs), typically include many regions of programmable logic that are interconnectable in any of many different ways by programmable interconnection resources. Each logic region is programmable to perform any of several logic functions on input signals applied to that region from the interconnection resources. As a result of the logic functions it performs, each logic region produces one or more output signals that are applied to the interconnection resources.
The interconnection resources typically include drivers, interconnection conductors, and programmable switches for selectively making connections between various interconnection conductors. The interconnection resources can generally be used to connect any logic region output to any logic region input; although to avoid having to devote a disproportionately large fraction of the device to interconnection resources, it is usually the case that only a subset of all possible interconnections can be made in any given programmed configuration of the programmable logic resource. Indeed, this last point is very important in the design of programmable logic resources because interconnection resources must always be somewhat limited in programmable logic resources having large logic capacity, and interconnection arrangements must therefore be provided that are flexible, efficient, and of adequate capacity without displacing excessive amounts of other resources such as logic.
Programmable logic resources also include memory regions, data registers, address registers, and digital signal processing (DSP) regions. The memory regions can be used as random access memory (RAM), read-only memory (ROM), content addressable memory (CAM), product term (p-term) logic, embedded array blocks (EABs), and other types of memories. The data registers can be used to route data and control signals. The address registers can be used to route signals to different addresses in the programmable logic resources. The DSP regions can be used for signal or data processing tasks.
The programmable logic resource typically includes circuitry such as conductors and connectors for providing interconnect resources between the programmable logic regions, memory regions, data registers, address registers, and DSP regions (e.g., special purpose hardware for implementing multiplication functions). In addition, global interconnect resources can be used to apply input signals to, and output signals from, the different regions.
Crossbars and barrel shifters are commonly used in programmable logic resources in many switching applications including, for example, local area network (LAN), asynchronous transfer mode (ATM), networking, telecommunications, digital signal processing, and multiprocessing systems. A crossbar reorders input data to send to its output. For example, in many networking applications, a crossbar receives an incoming burst of data that contains some data, such as a packet header, that is no longer needed once the data reaches the crossbar. The crossbar can then separate the unnecessary or invalid data from the valid data. A barrel shifter aligns data by shifting the data to an appropriate storage location. For example, when there are unused storage locations between two sets of data, the barrel shifter will shift the data to remove the unused storage locations.
Crossbars and barrel shifters are typically implemented using multiplexers. Multiplexers are well-known elements commonly used in logic circuitry. Known techniques for implementing a multiplexer generally rely on some aspect of decoding a control signal being sent to the multiplexer in order to determine which of the input signals should be selected as an output. Thus, additional decoding circuitry is used and additional clock cycles are required for the decoding process to complete.
A multiplexer is implemented in a programmable logic resource using lookup tables (“LUTs”) or logic elements (“LEs”), the inputs of which are sent into a logic gate that, in turn, outputs the output of the multiplexer. For example, a single four-input LUT (a common size implemented in commercial programmable logic resources) can be configured to implement a 2-input, 1-output (2:1) multiplexer by using one of the LUT's inputs as a selection criterion signal and two other inputs as input signals. To build more complex multiplexers, two or more LUTs can be coupled together using programmable connectors. For example, to implement a four-input, 1-output (4:1) multiplexer, three LUTs can be used. Two LUTs, each implementing a 2:1 multiplexer with a first selection criterion signal, can have its outputs coupled to the inputs of a third LUT that implements a 2:1 multiplexer with a second selection criterion signal. The output of the third LUT is the output of the 4:1 multiplexer.
Crossbars and barrel shifters require a large number of multiplexers to implement. Because modern networking applications require large amounts of crossbar selection and barrel shifter functionality in programmable logic resources, the current implementation of crossbars and barrel shifters in programmable logic resources is very inefficient because of the large requirement of logic elements.
In view of the foregoing, it would be desirable to provide a more efficient implementation of crossbars and/or barrel shifters in programmable logic resources.